The PROFINET Universal Industrial Communication Controller is completely written in VHDL and optimized for Xilinx® Zynq™-7000 All Programmable SoCs. Supporting advanced features like Dynamic Frame Packing, the IP core allows cycle times down to 31.25µs. The PROFINET IRT IP core, developed by InES, can easily be combined with other IP cores to build entire System on Chip (SoC) solutions.
IRT cycle times as low as 31.25 µs
Complete IEEE 1588 PTP implementation in hardware
400 MHz timestamp synchronization accuracy of 60 ns over 20 nodes
Isochronous traffic can completely bypass the software stack
Optimized for Xilinx Zynq
Compatible with all PROFINET stacks
Separate buffers for LLDP and DCP frames
IP legacy traffic as well as ART and RTA frames
Enclustra is a dynamic and innovative FPGA design service company located in Technopark Zurich, Switzerland.
With the FPGA Design Center, Enclustra provides services covering the whole range of FPGA-based system development: From high-speed hardware or HDL firmware through to embedded software, from specification and implementation through to prototype production.
In the FPGA Solution Center, Enclustra develops and markets highly-integrated FPGA modules and FPGA-optimised IP cores.
By specialising in forward-looking FPGA technology, and with a broad application knowledge, Enclustra can offer ideal solutions at minimal expense in many areas.