The two PHY ports on the DM8603 are IEEE 802.3u standards compliant. Aside for the first two PHY ports and in an effort for maximum application flexibility, the third port on the DM8603 offers the options to either connect with an MII, reversed MII, or RMII. The reversed MII configuration is used to connect with SoC’s with a MII interface. The RMII interface is the alternative interface configuration in case of the need to connect a lower pin count Ethernet PHY or SoC.
To maximize the performance of each port, the DM8603 was designed with a number of features. For proper bandwidth, each port also supports ingress and/or egress rate control. In support of efficient packet forwarding, the DM8603 has port-based VLAN with tag/un-tag functions for up to 16 groups of 802.1Q. Each port includes MIB counters, loop-back capability, built in memory self test (BIST) for the system, and board level diagnostic.
In designing for the requirements of various data, voice, and video applications, enough internal memory has been provided for usage of the DM8603’s three ports, and the internal memory supports up to 1K uni-cast MAC address table. Then to meet the demands of various bandwidth and latency issues in data, voice, and video applications, each port of the DM8603 has four priority transmit queues. These queues can be defined either through port-based operation, 802.1p VLAN, or the IP packet TOS field automatically.