14 - 16 March 2017 // Nuremberg, Germany

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APS25

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The APS25 32-bit processor core IP is aimed at high performance embedded system-on-chip (SoC) applications. The APS25 supports the creation of more complex processor subsystems with caches, coprocessors and multiple cores.

The APS25 CPU starts at around 19 kgates and includes a parallel multiplier and HW divider. The core design is optimised for high throughput and is capable of over 400 MHz with 90 nm geometries. The APS25 can be used in single-, dual- or multi-core configurations or in heterogeneous systems with other APS cores. The core supports the AXI4-Lite bus.

The core is supported with peripherals, bridges, software development tools and real time operating systems.

The APS25 is the natural choice for embedded applications that require good integer performance.

Features

  • 32-bit modern RISC architecture
  • Designed for C/C++
  • 16 registers
  • Up to 256 interrupts with up to 16 priority levels
  • From 18.8 kgates
  • 5-stage pipeline
  • 4 GB addressing
  • 2.28 DMIPS/MHz
  • 2.52 CoreMarks/MHz
  • Max clock frequency: 400 MHz, 90 nm
  • Dynamic power: 19 µW/MHz, 90 nm
  • AXI4-Lite bus
  • Standard peripherals (timers, counters, I2C, SPI, UART, GPIO, etc)
  • Ethernet 10/100, USB 2.0 and USB OTG peripherals
  • Optional instruction and data caches
  • Co-processor interface
  • Latency free interface to and from AHB Lite and to APB
  • Elipse-based IDE
  • Ports of FreeRTOS, OpenRTOS, Micrium µC/OSII® & µC/OSIII®, TargetOS and µC Linux

Applications

  • Advanced sensing applications
  • Dual- and multi-core systems
  • Encryption/decryption
  • Home automation
  • Wireless communication
  • Wireline communication
  • Embedded control

APS1

LOGO_APS1

APS3R

LOGO_APS3R

Cortus Development Platform

LOGO_Cortus Entwicklungsplatform

FPS26

LOGO_FPS26

APS25 is assigned to following product groups:

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