27 February - 1 March 2018 // Nuremberg, Germany

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Exhibitors & Products embedded world 2017
Zoom product LOGO_SoC and ASIC Development

SoC and ASIC Development

LOGO_SoC and ASIC Development

SoC and ASIC Development

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You need someone who will provide a complete portfolio from IC architecture to GDSII? Dream Chip Technologies has an average of 15 years SoC and ASIC design experience at your service – we are used to partition very complex RTL designs with millions of gates into multi-FPGA systems for validation and product development.

Our complete offering includes:

  • Concept & Feasibility studies
  • System specifications
  • Cost estimation and evaluation
  • Architecture and interface definition
  • IP selection, including Third Party IP
  • Implementation in VHDL or Verilog
  • Top Level and Functional Verification
  • Synthesis
  • FPGA mapping and validation
  • Place and Route
  • Layout
  • GDSII qualification
  • Foundry or FPGA selection
  • Chip delivery and logistics

We support the Cadence and Synopsys tool chains including the design in Verilog and VHDL as well as verification approaches like System Verilog/UVM and System C

Arria 10 SoC „System on Module“ SoM

LOGO_Arria 10 SoC „System on Module“ SoM

Embedded Software Development

LOGO_Embedded Software Entwicklung

FPGA and PCB Development

LOGO_FPGA und PCB Entwicklung

IP, Intellectual Property for FPGA and ASIC

LOGO_IP, Intellectual Property für FPGA und ASIC

SoC and ASIC Development is assigned to following product groups:


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