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Verification of RISC-V SoC Designs Using Formal Methods
Verification of system-on-chip (SoC) designs containing RISC-V processor cores is challenging. The cores can come from many sources, so they must be vetted for compliance to the instruction set architecture (ISA) specification. Beyond the ISA, optional features, custom extensions, and microarchitectural implementation must also be verified. The SoC team must guarantee proper integration of the cores and the entire chip must be screened for design issues that could hinder proper operation. Further, both cores and SoC must be checked thoroughly to ensure that no hardware Trojans or security risks are present. Only formal methods can provide full proofs for all these verification tasks and build confidence in the integrity of the design. This paper describes a formal-based methodology to meet these challenges, summarizes previous work on multiple RISC-V cores and SoCs, and presents previously unpublished results.
--- Datum: 25.02.2020 Uhrzeit: 15:00 - 15:30 Uhr Ort: Conference Counter NCC Ost