Konferenzen und Rahmenprogramm
The ParaNut/RISC-V Processor – An Open, Parallel, and Highly Scalable Processor Architecture for FPGA-based Systems
The paper presents a customizable, highly scalable and RISC-V compatible processor architecture for FPGA-based systems. A key aspect of the ParaNut architecture is a special concept of parallelism, which combines advantages of SIMD vectorization and simultaneous multi-threading in one architecture. At the same time, the complexity of a single computing core is minimized in order to save area and power. Speculation techniques are generally avoided in order to make the processor robust against security flaws such as Spectre and Meltdown. ParaNut/RISC-V processors are planned to be used in several application fields including computer vision, deep learning, and Internet of Things. The present implementation passes the RISC-V compliance tests (RV32IM instructions) and is thus compatible to the standard RISC-V toolchain. Preliminary experiments on a Xilinx 7 platform show 0.87 CoreMarks/MHz using 1 core and 3.47 CoreMarks/MHz using 4 cores, revealing an almost perfect speedup of 3.99.
--- Datum: 27.02.2020 Uhrzeit: 14:30 - 15:00 Uhr Ort: Conference Counter NCC Ost