Konferenzen und Rahmenprogramm
Leveraging the Scalability of the RISC-V ISA to Create Optimized MCU Designs
Modern domain specific designs require optimized area and features to deliver high efficiency and performance. A truly scalable processor architecture permits the design of MCU core that are scalable in pipeline depth, extension support, and other key features. In this talk, SiFive will demonstrate how to create a heterogeneous multi-core microcontroller that combines many powerful processor cores alongside simpler, low power essential cores that can be treated as a holistic entity by software and system design.
--- Datum: 27.02.2020 Uhrzeit: 13:30 - 14:00 Uhr Ort: Conference Counter NCC Ost