Konferenzen und Rahmenprogramm
FPGA-Design Using C/C++ and High-Level Synthesis
High-Level Synthesis (HLS) tools enable the implementation of algorithms coded in C/C++ as FPGA IP cores. Different RTL architectures can be generated by HLS tools in a short time and the tradeoff between performance and ressource usage can be explored. Furthermore the generated VHDL/Verilog code can be easily verified using the C/C++ testbench. Thus design productivity is substantially enhanced when compared to traditional VHDL/Verilog based design. This hands-on workshop will give an introduction in the design of IP cores for Xilinx FPGAs using the Vivado HLS tool. After an overview of the design flow with Vivado HLS it will be shown how the synthesis result can be interpreted in order to derive measures for optimizations. The influence of data types will be shown and how different interfaces can be easily implemented by using directives. Finally it will be shown how the RTL hardware architecture can be optimized using pipelining, loop unrolling and the optimization of arrays.
--- Datum: 27.02.2020 Uhrzeit: 9:30 - 16:30 Uhr Ort: Conference Counter NCC Ost