Konferenzen und Rahmenprogramm
FPGA-based Modelling of Aging Effects and Implementation of IP-Cores for Wear-Out-Detection
The presentation will give some background information on a SEU-TID IP-Core for monitoring of single events and aging effects especially for flash-based FPGAs using floating gate transistors. The concept was verified by real measurements in medical radiation environments. A new special implementation IP of a ring oscillator is used to show the asymmetrical degradation for TID sensitivity and charge loss of transistors. It was simulated with a real-number modelling methodology (VHDL-RNM). This special implementation is also applicable for ASICs and SRAM-FPGA technologies. In addition a new IP architecture was developed to detect also aging effects due to normal wear-out mechanisms like electrical and thermal stress and charge loss of floating gate transistors. The results of accelerated life and stress tests will be presented.
--- Datum: 26.02.2020 Uhrzeit: 12:00 - 12:30 Uhr Ort: Conference Counter NCC Ost