Embedded Co-debugging Made Easy with Intuitive Instrumented SoC FPGA

Due to the increasing complexity of SoC, rendering on-chip debug and design bring-up is more difficult and time-consuming. Conventionally, debugging the application running on an embedded multi-core CPUs is done using an IDE tool connected to the JTAG interface. With such IDE, a user often doesn€™t have controllability and observability of internal buses of the SoC. And very often they are limited by the JTAG bandwidth for real-time trigger, capture and in-situ intervention. This paper will show how developers can save time by using the SoC€™s in-built instrumentation to trigger and capture od desired AXI bus transactions between master-slave pairs like DMA to DDR. The developer can capture the instruction trace of multicore RISC -V processors based on the address range. The configuration can not only be achieved over JTAG but also done by using application running on the RISC-V processor. For large traces, the trace data can be routed to DDR memory or any memory connected to AXI slave.