Konferenzen und Rahmenprogramm
A Cycle-accurate Trace Approach for RISC-V Systems
RISC-V is being used in complex real-time heterogeneous systems. The software executing on such systems needs to be tuned to provide the best performance possible. Developers need insight into the operation of the software and its interaction with the underlying hardware structures, including NoCs and CPUs. A key element of this is cycle accurate processor trace, which provides information on how many cycles code takes to execute, whether there are stalls and dependencies and how long they last. System designers can use these insights to make optimizations and achieve efficiency gains. We present a cycle accurate instruction trace encoder algorithm which has been implemented using as the primary input the interface proposed in the RISC-V Processor Trace working group. The presentation will illustrate how the encoder€™s capabilities - including filtering, matching and SoC-wide cross-triggering - can be used to produce significant improvements in overall system performance.
--- Datum: 27.02.2020 Uhrzeit: 16:00 - 16:30 Uhr Ort: Conference Counter NCC Ost