Wir möchten auf unserer Internetseite Dienste von Drittanbietern nutzen, die uns helfen, unsere Werbeangebote zu verbessern (Marketing), die Nutzungsweise unserer Internetseite auszuwerten (Performance) und die Internetseite an Ihre Vorlieben anzupassen (Funktional). Für den Einsatz dieser Dienste benötigen wir Ihre Einwilligung, welche jederzeit widerrufen werden kann. Informationen zu den Diensten und eine Widerspruchsmöglichkeit finden Sie unter „Benutzerdefiniert“. Weitergehende Informationen finden Sie in unserer Datenschutzerklärung.
UltraSoC provides a toolkit of more than 30 different modules that the SoC system architect can use in a variety of ways. We support any mixture of licensed-in IP and custom logic designed in-house. The system architect and design team have complete freedom to choose which blocks to monitor and to what level of detail. UltraSoC uses a message-based architecture that makes it entirely “host interface agnostic”. Modules range from dedicated, optimized IP to highly parametrized modules that are configurable at design-time and run-time.
Bus performance monitor with trace
Passively monitors a master or slave interface on a bus, point-to-point fabric or on-chip network such as AXI, AXI4, or OCP 2.1. Also supports coherent protocols such as ACE and OCP 3.0 and packet-based interfaces like AMBA 5 CHI, and is easily adaptable to proprietary interconnects. Sophisticated filtering allows monitoring of end-to-end metrics such as bus cycles, transactions, duration, latency and hesitancy. Also allows debugging of bus hangs and error transactions.
A parametrized module that enables a wide variety of monitoring functions, including event and message generation, counting, accumulating and data trace, in response to system states or other conditions or sequences.
Processor advanced modules
Interfaces to processors and their proprietary debug resources (e.g. CoreSight). There are variants for ARM cores (including Cortex-A, -R, and -M), Cadence (Tensilica XTensa) and MIPS processors, allowing access to standard features such as run-control, breakpoint and watch-point resources, cross-triggering, and performance monitoring (eg cache hits). The module can be collocated and directly coupled with a processor or group to offload debug communication from the proprietary debug-interconnect and allow a truly scalable debug solution. Alternatively it can be indirectly coupled using an existing infrastructure such as ARM’s CoreSight.
Software instrumentation module
Allows data delivered over a bus fabric such as AXI to be automatically converted to UltraDebug instrumentation trace messages and transferred to the host debugger. The typical use case is to collect trace data from user APIs such as those from an OS. Supports time-stamping and cross-triggering with other modules.
Virtual console module
A peripheral interface that enables the system software to communicate bi-directionally with the debug host (generally running third-party development tools) via UltraSoC.
Debug DMA module
Provides memory access, enabling the debugger to read or write a block of memory via a bus fabric such as AXI, APB or OCP, in response to UltraSoC messages or events when preconfigured with a transfer description.
JTAG master module
Allows control of the IEEE1149.1 JTAG TAP from UltraSoC messages instead of from chip pins. Can be used to access and control IP components that are limited to access over JTAG, and enable power-on-self-test and other scan-based debug activities
System memory buffer module
Allows storage of debug messages in system memory using a bus interface like AXI.
Utility (GPIO) module
Connectivity module allowing the conversion of events into I/O signals that can be used internally or wired to chip I/O pins to enable interaction with external tools such as oscilloscopes.
Drives UltraSoC messages into an alternative debug system’s trace funnel for export to an external parallel port or high-speed serial interface. Versions are available for ARM’s CoreSight (ATB Communicator), MIPS’s PDTrace (MPDT Communicator), external parallel port interfaces, in-house trace solutions or AXI4 streaming interface.
Internal bus communicator
Enables software running inside the chip to actively drive UltraSoC through a bus slave as though it were the host debugger, allowing the software to “monitor itself” during pre-deployment testing and post-deployment / early-adoption.
Message engine and message hub modules
Universal blocks that can be connected hierarchically to form an on-chip debug fabric with a tree topology based on the UltraSoC message interface. Prioritize and route messages and real-time events between their interfaces and provide optional features such as buffering and shared security services.
A non-blocking message-based interconnect for joining the debug hierarchies of multiple sub-systems into a large-scale system in a variety of topologies (e.g. a ring). This is especially useful in larger SoCs, and with sub-systems in different power domains or clock domains.
Message slice module
Used to break the combinatorial path between one message interface and another by registering the signals in each direction. Aids timing closure by breaking a long link into two shorter links.
Provides debugger connectivity to UltraSoC via an IEEE 1149.1 scan-test interface.
Connects directly to an on-chip USB PHY to enable interconnection with the debug host at a much higher speed than would be possible using a traditional serial interface. Autonomous, requiring no host processor or software intervention. Optionally there is a hub component enabling the system to simultaneously use the same physical interface without processor intervention.
Leider gibt es für diesen Aussteller kein deutsches Firmenprofil.
UltraSoC is a pioneering technology start-up based in Cambridge, UK.
Our products put intelligent self-analytic capabilities in the systems-on-chip (SoCs) at the heart of today’s consumer electronic, computing and communications products.
Our embedded analytics technology helps solve the most pressing problems faced by the high-tech industries today – including cybersecurity, functional safety, and the management of complexity. Our solutions also allow designers to develop SoCs – the driving force behind both performance improvement and cost reduction in the electronics business – more quickly and cost-effectively.
UltraSoC’s flagship product line is a suite of semiconductor IP that puts an intelligent analytics infrastructure into the core hardware of an SoC. This provides intimate visibility of the real-world behavior of entire systems. The ultimate benefits include robustness against malicious intrusions; enhanced product safety; reduced system power consumption; and overall better performance – with fine-tuning of end products even after they are deployed in the field. These capabilities address applications in a broad range of market sectors, from automotive and IoT products, to at-scale computing and communications infrastructure.
Our products are used by leading names including Seagate Technology, HiSilicon (Huawei), Intel, Microchip Technologies, Alibaba group company C-SKY, and leading IT systems integrator Kraftway to bring these proven hardware-embedded benefits to their customers. Our partners include Andes, Arm, Cadence/Tensilica, CEVA, Esperanto, Imperas, Lauterbach, Mentor, MIPS, Moortec, Percepio, Segger, SiFive, Sondrel, and Teledyne LeCroy.
UltraSoC’s technology also has a substantial impact on the increasingly-pressurized economics of the semiconductor industry. Traditional SoC development methodologies have failed to keep pace with escalating systemic complexity, creating a ‘productivity gap’. Our intelligent analytics technology closes that gap, giving engineering teams actionable insights that shorten the total development cycle time, accelerate debug, and reduce risk and cost to ensure timely market entry. Analysis from SemiCo research demonstrates the bottom-line value of this approach – SoC design teams can double their profitability and reduce their development costs by a quarter by using UltraSoC.
UltraSoC is an active member of the RISC-V consortium, which aims to encourage the use of a new open source processor architecture which has been dubbed “the Linux of semiconductors”.
The company was named one of the 100 most exciting companies in the UK in the 2016 Mishcon de Reya / CityAM “Leap 100” list, and by Gartner as one of its 2016 “Cool Vendors”. It was recognized as “Best New Company” in the 2015 ELEKTRA Awards.