TOPIC Embedded Products has developed an operating system that will significantly reduce the development time and cost of creating products based on FPGA+processor combinations, like the ZYNQ® of Xilinx. Our Dyplo system’s OS bridges the gap between hardware and software design, and provides a means to enable a fully software-driven development flow.
Dyplo extensively uses partial reconfiguration; an advanced design technique in which the FPGA fabric can (partially and selectively) change its hardware configuration on the fly. This allows for execution of different functions re-using the same FPGA fabric over time. Dyplo manages the reconfigurable blocks such that functions can be executed as desired, either in software or in hardware, depending on the execution context constraints, such as power consumption, performance etc.
Boost your business
Companies are increasingly turning to combined microprocessor-FPGA solutions to increase the performance of their products. At the same time they are striving to reduce their time-to-market, as well as reducing their development cost to be more competitive.
DYPLO is an enabler to meet these challenges, helping companies to focus on developing the added value of their products while at the same time realizing up to 30% savings in development effort!
Applying DYPLO in your development cycle provides opportunities for
Reduction of Time-to-Market
Reduction of development effort
Reduction of Bill-of-Materials
Push your product development
DYPLO is a middleware solution to enable seamless integration of FPGA and software processes in applications. DYPLO links processes, executed on processor(s) and FPGA(s), with scalable software and hardware data streams embedded in the applied operating system. DYPLO managed processes, executed on FPGA fabric, share the same characteristics as software executed processes due to the extensive usage and support for partial reconfiguration, an advanced technology available in FPGAs.
Applying DYPLO on your development process provides opportunities for
Accelerated system development using the operating system for ARM®+FPGA
Software driven hardware development
Managed partial reconfiguration
Easy integration of (existing) IP-blocks (through use of AXI4 interfaces)