Silexica provides a complete parallel software development tool suite for programming complex multicore applications. Write software without the need to understand low-level hardware platform details. Focus on your design goals and meet your deadlines. Leave tedious and error-prone code partitioning, software task distribution, and communication/synchronization code generation to Silexica´s automated multicore mapping tools. Achieve optimal hardware resource utilization and first-time-right parallel software implementations.
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SLX Explorer is a flexible, retargetable version of the SLX Mapper with an user-editable abstract multicore model for hardware and software system architects. Its flexibility serves two main use cases. On one hand, it enables architects to search for the best-suited off-the-shelf multicore platform for a given application. On the other hand, it allows to perform "what if" analysis with respect to software and hardware changes to drive exploration, design, and evolution for next generation multicore systems. Examples of what-if queries include (i) analyzing the effects of hypothetical changes in the application workload due to upcoming radio or multimedia standards and (ii) analyzing the effects on application performance of adding processors, memories, and hardware accelerators onthe current multicore architecture. SLX Explorer employs Silexica's abstract platform model and proprietary parallel performance estimation technology, enabling turn-around times 2-3 orders of magnitude faster than state-of-the-art instruction-set simulators.
The SLX Generator uses unique source-to-source compiler technology to produce highly optimized C Code for the individual processors of the target multicore. It receives the optimized software distribution computed by the SLX Mapper and automatically selects the best APIs for task management, synchronization, and communication. The generated C code is tailored for each individual processor, according to the mapping decisions. The output of the SLX Generator can be directly compiled with the individual native C compiler toolchains of the cores in a heterogeneous multicore. The base version of the SLX Generator includes standard parallel programming interfaces such as, Pthreads, SystemC, and MPI. These standard programming models can be used for fast functional software verification on the development host machine. Further versions of SLX Generator are currently available for selected off-the-shelf multicore platforms. New SLX Generator backends may be jointly developed with the customer upon request.
SLX Mapper receives as input a parallel application specification in form of a process network. This formalism is a natural way to represent streaming applications, and it covers a wide range of dataflow models. With process networks, the application is represented as a collection of processes that communicate over logical buffered channels. The SLX Mapper analyzes the computation and communication patterns of the process network and uses advanced optimization techniques to automatically select (i) the optimal mapping of processes to cores, (ii) the fastest mapping of logical channels to platform memories, and (iii) the most effective memory allocation for the buffers used for inter-process communication. Additionally, the user can specify real-time and resource constraints which are taken into account when computing a solution. Internally, SLX Mapper uses an abstract model of the target multicore architecture as well as fast and accurate software performance estimation technologies. Optionally, measured or estimated power consumption can be used together with performance to drive the mapping optimization within the SLX Mapper. As a final output, the SLX Mapper produces a complete spatial and temporal application mapping that can be forwarded to the SLX Generator, or to the customer's in-house code generator backend.
SLX Parallelizer receives sequential C code as input and semi-automatically turns it into a parallel process network implementation. Internally, it uses static and dynamic code analysis techniques to detect parallelism patterns that are guaranteed to deliver performance improvements in multicores. Example of these patterns areTask-Level Parallelism (TLP), Data-Level Parallelism (DLP) and Pipeline-Level Parallelism (PLP). This structured parallelism is commonly present in multimedia and signal processing applications but is mostly hidden within the sequential implementation. SLX Parallelizer interacts with the programmer to expose this parallelism and performs whole-program analysis and optimizations to decide on the best parallel representation of the application for a given target multicore. The parallelized version can be exported as C code with standard parallel APIs, such as pthreads or MPI, or can be forwarded as a CPN process network into the SLX Mapper for further optimizations and refinement.